1. Field of the Invention
This disclosure relates to power-on-reset circuits, and more particularly to a power-on-reset circuit employing a current mirror for a more precise trip point at low supply voltages. The power-on-reset circuit of the present invention may be part of an integrated circuit device such as a microprocessor.
2. Description of the Relevant Art
When power is first supplied to an electronic device, it is often desirable to hold the device in a reset state until the power supply is stable. Typically as a power supply ramps up, the voltage may fluctuate for a certain period of time until the power reaches a stable operating voltage. If an electronic device is not held in reset during this power ramp up period, the device will not perform correctly and could even be damaged. Typically a power-on-reset circuit is provided to hold the rest of the electronic device in a reset state until the power reaches a safe operating voltage. Typically a power-on-reset circuit provides a power-on signal, which may be the reset signal for an integrated circuit device, that indicates when the power supply has reached a safe minimum operating voltage. The power-on-reset circuit must keep the power-on signal unasserted until the supply voltage reaches the appropriate level. At that point, the power-on-reset circuit asserts the power-on signal to allow the integrated circuit device to begin operation. Therefore, the basic requirement for the power-on-reset circuit is to assure that the power-on signal is unasserted when the voltage is below the minimum safe operating voltage and is asserted when the voltage is above the minimum safe operating voltage. The design with an acceptable power-on-reset circuit is problematic, however, since typically the power-on-reset circuit is also powered by the same supply voltage that it is monitoring. The power-on-reset circuit must be able to appropriately drive the power-on signal as the supply voltage ramps up. Correct power-on-reset operation is especially important in an integrated circuit device such as a microprocessor. If the microprocessor begins operation before the power supply is stable, then the microprocessor may be damaged, cause data to be lost, or operate in an incorrect state.
FIG. 1 is a schematic diagram of a conventional power-on-reset circuit. PMOS transistors 14 and 16 are source-connected to supply voltage 10. The drains of PMOS transistors 14 and 16 are connected to the input of a first inverter 28. Resistor 18 is also connected to input node of inverter 28. The other end of resistor 18 is connected to ground node 12. Inverter 28 is connected in series with three more inverters, 30, 32 and 34. Thus, the output of inverter 28 is connected to the input of inverter 30, and the output of inverter 30 is connected to the input of inverter 32, and the output of inverter 32 is connected to the input of inverter 34. Inverter 34 outputs power-on signal 36. The gate of PMOS transistor 14 is connected to the drain of PMOS transistor 14 which is also connected to the input node for inverter 28. The gate of PMOS transistor 16 is connected to the output of inverter 28. The drain of NMOS transistor 20 is also connected to the input of inverter 28. The drains of NMOS transistors 22 and 24 are connected to the gate of NMOS transistor 20 and the sources of NMOS transistors 20, 22 and 24 are connected to ground node 12. The gate of NMOS transistor 22 is also connected to the gate of NMOS transistor 20 which is further connected to the drain of PMOS transistor 26. The source of PMOS transistor 26 is connected to the output of inverter 28 which is also connected to the gate of PMOS transistor 16. The gates of PMOS transistor 26 and NMOS transistor 24 are connected to the output of inverter 30.
The operation of the power-on-reset circuit of FIG. 1 is described as follows. PMOS transistor 14 begins to conduct current as supply voltage 10 ramps up above the threshold voltage of PMOS transistor 14. This current begins to charge the input node to inverter 28. When the supply voltage reaches a certain level, inverter 28 will flip and drive its output low. When inverter 28 flips to a low voltage, inverters 30, 32 and 34 will change state resulting in a power-on signal 36 being asserted. Also, PMOS transistor 16 will be turned on hard, pulling the input to inverter 28 up to approximately the full supply voltage. NMOS transistors 20, 22 and 24 and PMOS transistor 26 are configured to perform a Schmitt trigger function that delays the voltage input level at which inverter 28 changes state. Therefore, instead of changing state at approximately the supply voltage divided by two, inverter 28 will change state at a voltage level somewhat greater than that, such as 2/3 of the supply voltage. Therefore, as the supply voltage 10 ramps up, the power-on-reset circuit will assert the power-on signal when the voltage at the input node to inverter 28 reaches the trip point of inverter 28 as adjusted by the delay circuit comprised of NMOS transistors 20, 22, 24 and PMOS transistor 26.
For the power-on-reset circuit to operate correctly, there must be some margin between the voltage at which inverter 28 changes state, or flips, and the minimum operating voltage for the device. However, an ideal power-on-reset circuit will assert the power-on signal at the minimum operating voltage level for the device. Another problem for the power-on-reset circuit of FIG. 1 is that the trip point for the circuit is dependent upon the supply voltage level since the flip point for inverter 1 is dependent upon the supply voltage. The power-on-reset circuit is designed to function as a supply voltage is ramping up. Therefore, it is difficult to design a power-on-reset circuit to have a precise and accurate trip point since the trip point is a function of the supply voltage, which is changing in value. Ideally, a power-on-reset circuit should have a trip point that is precisely and accurately defined as approximately the minimum operating voltage for the device. Another problem with the power-on-reset circuit of FIG. 1 is that there is a constant current drain through PMOS transistor 16 and resistor 18 because PMOS transistor 16 remains turned on after power ramps up. This constant current flow through resistor R1 increases overall power consumption. Also, the current flow at static conditions through PMOS transistor 16 and resistor 18 may create problems for I.sub.ddq testing. The current flow may erroneously indicate a stuck at fault during I.sub.ddq testing.
Therefore, it is desirable to have a power-on-reset circuit that indicates when the supply voltage in an electronic device is at or above the minimum operating voltage for the device. It is further desirable that the trip point at which the power-on-reset circuit asserts the power-on signal to indicate that the supply voltage is at or above the minimum operating level be precisely and accurately located at the minimum operating voltage level. Furthermore, the power-on-reset circuit should have little or no power consumption by the current draw at static conditions. It is desirable that the power-on-reset circuit not indicate erroneous faults during testing such as I.sub.ddq testing.